Roadmap for nanometer ultra-low-power digital circuits based on sub/near-threshold CMOS logic

For a decade, low-power design has been part of mainstream semiconductor R&D activities, while ultra-lowpower (ULP) design remained dedicated to niche markets of particular applications such as sensor networks, RFIDs and biomedical devices, where speed performances are not critical. However, today’s 65/45nm CMOS technologies offer so compact circuits and high device performance that they give the opportunity for the designers to trade Silicon die area for energy efficiency, while maintaining sufficient speed. As a consequence, ultra-low-power design is now an emerging solution for energy-efficient mainstream electronics applications both in the consumer and professional markets. An important trend for designing ultra-low-power circutis is to aggressively scale the supply voltage Vdd to sub or near-threshold regime. In this document, we summarize the conclusions from the work carried out at the Université catholique de Louvain in this field, to set up a possible roadmap for sub/near-threshold CMOS logic in nanometer technologies.